Analog Electronic Circuits Laboratory Viva Questions 1

Theory_Questions:

1. The slope of VDS-IDS characteristics of a FET is controlled by a

(A) VGS
(B) IDS
(C) VDS
(D) Both (A) & (B)
(E) None

Answer: [A] VGS

2. What is the condition for compensating the nonlinearity in VDS-IDS characteristics of a FET?
 VGS Is the gate to source voltage,VDS is the drain to source voltage.

(A) VGS < ( VDS / 2 ) + ( VControl / 2 )
(B) VGS < ( VGS/ 2 ) - ( VControl / 2 )
(C) VGS = ( VDS / 2 ) + ( VControl / 2 )
(D) VGS = ( VGS / 2 ) + ( VControl / 2 )
(E) VGS < ( VDS / 2 ) - ( VControl / 2 )

Answer: [C] VGS = ( VDS / 2 ) + ( VControl / 2 )

3.  What will be the input voltage Vi to a FET, for V0 is VDD.

(A) Vi  > VT
(B) Vi  >= VT
(C) Vi  <= VT
(D) Vi  = 0 v

Answer: [C] Vi  <= VT

4. Which of the following condition is correct, if a FET is operating in the amplification region?

(A) VGSQ <= Vi  - VT
(B) VGSQ <= Vi  + VT
(C) VGSQ >= Vi  - VT
(D) VGSQ >= Vi  + VT

Answer: [C] VGSQ >= Vi  - VT

5. Which of the following statement(s) is (are) correct?

(A) In designing a digital circuit, all conventional resistors are replaced by MOS resistors
(B) In designing a digital circuit, some conventional resistors are replaced by MOS resistors
(C) In designing a digital circuit, all conventional resistors are not replaced by MOS resistors
(D) None of the above

Answer: [A]  In designing a digital circuit, all conventional resistors are replaced by MOS resistors

6. For a NMOS inverter, if the gate to source voltage is 0 V, what will be the output voltage?

(A) VGS
(B) VDD
(C) VGD
(D) Both (A) & (B)
(E) None

Answer: [D] Both (A) & (B)

7.  What is the level of IG in an FET?

(A) Zero amperes
(B) Equal to ID
(C) Depends on VDS
(D) Undefined

Answer: [A] Zero amperes

8. What will be the range of input impedance of a FET?

(A) 10 Ω to 1 KΩ
(B) 1 KΩ to 10 KΩ
(C) 10 KΩ to 50 KΩ
(D) 1 MΩ to several hundreds of MΩ

Answer: [B] 1 KΩ to 10 KΩ

Problematic_Questions:

9. The drain resistance of a FET (Common source configuration) is, RD = 1KΩ, gm= 40 milli Siemens then what is the gain of this amplifier?

(A) 250
(B) -250
(C) 40
(D) -40
(E) 250000
(F)-250000

Answer: [A] -250

10.  Gate to source voltage of a particular FET is given by VGSQ = 4 V and VT = 2 V. In order to
 have a 1% distortion in the output, what could be the possible value of input peak voltage?

(A) 40 mV
(B) 90 mV
(C) 120 mV
(D) 100 mV
(E) 200 mV
(F) 300 mV

Answer: [D] 100 mV


Analog Electronic Circuits Laboratory Viva Questions 1
Analog Electronic Circuits Laboratory Viva Questions 2
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